1. Statement of the Technical Field
The inventive arrangements relate to forward error correction code encoders. More particularly, the present invention relates to an encoder for Low Density Parity Check (LDPC) codes with particular structural features, allowing for long block lengths and high throughput rates.
2. Description of the Related Art
There are many types of forward error correction codes (FECCs) known in the art. One such type of FECC is a Low Density Parity Check (LDPC) code. A detailed description of LDPC codes can be found in “Low Density Party-Check Codes”, M.I.T. Press, 1963, written by Robert G. Gallager. The entire disclosure of this publication is incorporated herein by reference. An LDPC code can allow error free transmission of data across a channel at close to the theoretical limit of a channel capacity. LDPC codes were not used at the time of their creation (i.e., 1960) because encoder and decoder implementations were not reasonably practical. However, there have been many developments in the field of electronics and computer science that allow for a reasonably practical implementation of algorithms for generating LDPC codes.
There are several approaches which have emerged for generating FECC codes having good performance characteristics. One such approach involves designing LDPC codes using bit flipping. A detailed description of this approach can be found in “Designing LDPC Codes Using Sit Flipping”, Proceeding international Conference Communications, Helsinki, Finland, pp. 55-59, 2001, written by J. Campello, D. S. Modha, and S. Rajagopalan. The entire disclosure of this publication is incorporated herein by reference. Another such approach involves implementation of a progressive edge growth (PEG) algorithm. A detailed description of this approach can foe found in “Progressive Edge-Growth Tanner Graphs”, Proceeding IEEE Global Telecommunications Conference, vol. 2, pp. 995-1001, November 2001, written by X. Y, Hu, E. Eleftheriou, and D. M. Arnold. The entire disclosure of this publication is also incorporated herein by reference.
Despite the advantages of these approaches, they suffer from certain drawbacks. For example, these approaches do not provide optimized hardware and/or software implementations of an algorithm for generating an FECC code. For example: the PEG algorithm can be used in an IEEE 802.16 Broadband Wireless Access standard application. In such a scenario, the parity check code generated using the PEG algorithm has a relatively short block length. This short block length is due to the complexity of the hardware implementation of the PEG algorithm. The complex hardware implementation of the PEG algorithm can provide a relatively low data throughput rate feature to the Broadband communications system.
Significantly, the conventional hardware implementations for LDPC encoders are generally optimized for relatively short block lengths. For example, relatively short block lengths can include code blocks having a length less than about 10 kilo-bits. But it should be noted that the effectiveness of these LDPC codes improves dramatically with increasing block length. Such conventional hardware implementations for LDPC encoders do not provide a practical means for handling block lengths in the range greater than about 10 kilo-bits.
In view of the forgoing, there is a need for a practical hardware implementation of an algorithm for generating an LDPC code. There is also a need for a hardware implementation of an algorithm for generating an LDPC code with a long block length. There is further a need for a hardware implementation of an LDPC algorithm having a relatively high data throughput rate feature.